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This book is a revised version of the PhD dissertation written by the author at the Free University of Bozen-Bolzano in Italy. It presents a new approach to safety verification of a particular class of infinite-state systems, called Data-Aware Processes (DAPs). To do so, the developed technical machinery requires to devise novel results for uniform interpolation and its combination in the context of automated reasoning. These results are then applied to the analysis of concrete business processes enriched with real data. In 2022, the PhD dissertation won the “BPM Dissertation Award”, granted to outstanding PhD theses in the field of Business Process Management.

This book is a revised version of the PhD dissertation written by the author at the Free University of Bozen-Bolzano in Italy. It presents a new approach to safety verification of a particular class of infinite-state systems, called Data-Aware Processes (DAPs). To do so, the developed technical machinery requires to devise novel results for uniform interpolation and its combination in the context of automated reasoning. These results are then applied to the analysis of concrete business processes enriched with real data. In 2022, the PhD dissertation won the “BPM Dissertation Award”, granted to outstanding PhD theses in the field of Business Process Management.

System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).

System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).

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This book introduces the concepts of identifiability and observability in mathematical epidemiology, as well as those of observers’ constructions. It first exposes and illustrates on several examples the mathematical definitions and properties of observability and identifiability. A chapter is dedicated to the well-known Kermack McKendrick model, for which the complete analysis of identifiability and observability is not available in the literature. Then, several techniques of observer constructions, in view of online estimation of state and parameters, are presented and deployed on several models. New developments relevant for applications in epidemiology are also given. Finally, practical considerations are discussed with data and numerical simulations related to models previously analysed in the book. The book will be appealing to epidemiological modellers and mathematicians working on models in epidemiology.This book contributes to Sustainable Development Goal 3 (SDG3): Good Health and Well Being.

This book introduces the concepts of identifiability and observability in mathematical epidemiology, as well as those of observers’ constructions. It first exposes and illustrates on several examples the mathematical definitions and properties of observability and identifiability. A chapter is dedicated to the well-known Kermack McKendrick model, for which the complete analysis of identifiability and observability is not available in the literature. Then, several techniques of observer constructions, in view of online estimation of state and parameters, are presented and deployed on several models. New developments relevant for applications in epidemiology are also given. Finally, practical considerations are discussed with data and numerical simulations related to models previously analysed in the book. The book will be appealing to epidemiological modellers and mathematicians working on models in epidemiology.This book contributes to Sustainable Development Goal 3 (SDG3): Good Health and Well Being.

This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine.  Additionally, the design flow described is applied to a broad variety of validation and verification tasks.  The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow. 

This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine.  Additionally, the design flow described is applied to a broad variety of validation and verification tasks.  The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow. 

This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine.  Additionally, the design flow described is applied to a broad variety of validation and verification tasks.  The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow. 

This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016.  The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design.

This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016.  The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design.

This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016.  The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design.

This book portrays an extensive and intensive discussion of theories and research that refer to Vygotsky’s and Feuerstein’s theories of mediated learning and their effects on learning potential and cognitive modifiability. Most topics are discussed in relation to a broad spectrum of developmental and cognitive research that are under the conceptual umbrella of mediated learning and cognitive modifiability. Some topics such as neural plasticity, executive functions, mental rotation, and cognitive education are related to mediated learning, though indirectly, and therefore are included in this book. In many ways the book presents an extension of Vygotsky and Feuerstein’s theories and empirical validation in a variety of family, social and cultural contexts. The book includes a thorough analysis and summary of 50 years of research and methodology of the intimate relation between mediated learning interactions and cognitive modifiability and of dynamic assessment underlying measurement of cognitive modifiability. Special emphasis is given to Tzuriel’s dynamic assessment instruments developed during more than four decades. Tzuriel’s novel instruments are interwoven in the extensive research on parent-child interactions, siblings’ , teachers' and peers' mediation and in validation of dynamic assessment approach and cognitive education programs aimed at development of thinking skills and academic achievements.

This book portrays an extensive and intensive discussion of theories and research that refer to Vygotsky’s and Feuerstein’s theories of mediated learning and their effects on learning potential and cognitive modifiability. Most topics are discussed in relation to a broad spectrum of developmental and cognitive research that are under the conceptual umbrella of mediated learning and cognitive modifiability. Some topics such as neural plasticity, executive functions, mental rotation, and cognitive education are related to mediated learning, though indirectly, and therefore are included in this book. In many ways the book presents an extension of Vygotsky and Feuerstein’s theories and empirical validation in a variety of family, social and cultural contexts. The book includes a thorough analysis and summary of 50 years of research and methodology of the intimate relation between mediated learning interactions and cognitive modifiability and of dynamic assessment underlying measurement of cognitive modifiability. Special emphasis is given to Tzuriel’s dynamic assessment instruments developed during more than four decades. Tzuriel’s novel instruments are interwoven in the extensive research on parent-child interactions, siblings’ , teachers' and peers' mediation and in validation of dynamic assessment approach and cognitive education programs aimed at development of thinking skills and academic achievements.